[PATCH] [3/3] x86_64: mce_amd support for family 0x10 processors

shin, jacob jacob.shin at amd.com
Wed May 17 20:22:49 CEST 2006


Add support for mce threshold registers found in future
AMD family 0x10 processor.  Backwards compatible with
family 0x0F hardware.

Signed-off-by: Jacob Shin <jacob.shin at amd.com>

---

 arch/x86_64/kernel/mce_amd.c |  402 +++++++++++++++++++++++++++++++------------
 include/asm-x86_64/mce.h     |   13 +
 2 files changed, 310 insertions(+), 105 deletions(-)

---

diff -uparN linux.orig/arch/x86_64/kernel/mce_amd.c linux/arch/x86_64/kernel/mce_amd.c
--- linux.orig/arch/x86_64/kernel/mce_amd.c	2006-05-17 11:23:17.000000000 -0500
+++ linux/arch/x86_64/kernel/mce_amd.c	2006-05-17 11:27:55.000000000 -0500
@@ -1,5 +1,5 @@
 /*
- *  (c) 2005 Advanced Micro Devices, Inc.
+ *  (c) 2005, 2006 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
@@ -8,9 +8,10 @@
  *
  *  Support : jacob.shin at amd.com
  *
- *  MC4_MISC0 DRAM ECC Error Threshold available under AMD K8 Rev F.
- *  MC4_MISC0 exists per physical processor.
+ *  April 2006
+ *     - added support for AMD Family 0x10 processors
  *
+ *  All MC4_MISCi registers are shared between multi-cores
  */
 
 #include <linux/cpu.h>
@@ -29,32 +30,52 @@
 #include <asm/percpu.h>
 #include <asm/idle.h>
 
-#define PFX "mce_threshold: "
-#define VERSION "version 1.0.10"
-#define NR_BANKS 5
-#define THRESHOLD_MAX 0xFFF
-#define INT_TYPE_APIC 0x00020000
-#define MASK_VALID_HI 0x80000000
-#define MASK_LVTOFF_HI 0x00F00000
-#define MASK_COUNT_EN_HI 0x00080000
-#define MASK_INT_TYPE_HI 0x00060000
-#define MASK_OVERFLOW_HI 0x00010000
+#define PFX     "mce_threshold: "
+#define VERSION "version 1.1.0"
+
+#define NR_BANKS  6
+#define NR_BLOCKS 9
+
+#define THRESHOLD_MAX     0xFFF
+#define INT_TYPE_APIC     0x00020000
+
+#define MASK_VALID_HI     0x80000000
+#define MASK_LVTOFF_HI    0x00F00000
+#define MASK_COUNT_EN_HI  0x00080000
+#define MASK_INT_TYPE_HI  0x00060000
+#define MASK_OVERFLOW_HI  0x00010000
 #define MASK_ERR_COUNT_HI 0x00000FFF
-#define MASK_OVERFLOW 0x0001000000000000L
 
-struct threshold_bank {
+#define MASK_BLKPTR_LO    0xFF000000
+
+#define MCG_XBLK_ADDR     0xC0000400
+
+struct threshold_block {
+	unsigned int block;
+	unsigned int bank;
 	unsigned int cpu;
-	u8 bank;
-	u8 interrupt_enable;
+	u32 address;
+	u16 interrupt_enable;
 	u16 threshold_limit;
 	struct kobject kobj;
+	struct list_head miscj;
 };
 
-static struct threshold_bank threshold_defaults = {
+/* defaults used early on boot */
+static struct threshold_block threshold_defaults = {
 	.interrupt_enable = 0,
 	.threshold_limit = THRESHOLD_MAX,
 };
 
+struct threshold_bank {
+	struct kobject kobj;
+	struct threshold_block *blocks;
+	unsigned int sibling_count;
+};
+static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
+
+static DECLARE_MUTEX(threshold_lock);	/* serialize sysfs create/remove */
+
 #ifdef CONFIG_SMP
 static unsigned char shared_bank[NR_BANKS] = {
 	0, 0, 0, 0, 1
@@ -68,12 +89,12 @@ static DEFINE_PER_CPU(unsigned char, ban
  */
 
 /* must be called with correct cpu affinity */
-static void threshold_restart_bank(struct threshold_bank *b,
+static void threshold_restart_bank(struct threshold_block *b,
 				   int reset, u16 old_limit)
 {
 	u32 mci_misc_hi, mci_misc_lo;
 
-	rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
+	rdmsr(b->address, mci_misc_lo, mci_misc_hi);
 
 	if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
 		reset = 1;	/* limit cannot be lower than err count */
@@ -94,35 +115,55 @@ static void threshold_restart_bank(struc
 	    (mci_misc_hi &= ~MASK_INT_TYPE_HI);
 
 	mci_misc_hi |= MASK_COUNT_EN_HI;
-	wrmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
+	wrmsr(b->address, mci_misc_lo, mci_misc_hi);
 }
 
+/* cpu init entry point, called from mce.c with preempt off */
 void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
-	int bank;
-	u32 mci_misc_lo, mci_misc_hi;
+	u32 low, high, address;
+	unsigned int bank, block;
 	unsigned int cpu = smp_processor_id();
 
 	for (bank = 0; bank < NR_BANKS; ++bank) {
-		rdmsr(MSR_IA32_MC0_MISC + bank * 4, mci_misc_lo, mci_misc_hi);
+		block = 0;
+		address = MSR_IA32_MC0_MISC + bank * 4;
 
-		/* !valid, !counter present, bios locked */
-		if (!(mci_misc_hi & MASK_VALID_HI) ||
-		    !(mci_misc_hi & MASK_VALID_HI >> 1) ||
-		    (mci_misc_hi & MASK_VALID_HI >> 2))
-			continue;
+		do {
+			if (rdmsr_safe(address, &low, &high))
+				continue;
 
-		per_cpu(bank_map, cpu) |= (1 << bank);
+			if (!(high & MASK_VALID_HI)) { /* not valid */
+				if (block)
+					continue;
+				else
+					break;
+			}
+			    
+			if (!(high & MASK_VALID_HI >> 1)  || /* no counter  */
+			     (high & MASK_VALID_HI >> 2))    /* BIOS locked */
+				continue;
 
+			per_cpu(bank_map, cpu) |= (1 << bank);
 #ifdef CONFIG_SMP
-		if (shared_bank[bank] && cpu_core_id[cpu])
-			continue;
+			if (shared_bank[bank] && cpu_core_id[cpu])
+				continue;
 #endif
-
-		setup_threshold_lvt((mci_misc_hi & MASK_LVTOFF_HI) >> 20);
-		threshold_defaults.cpu = cpu;
-		threshold_defaults.bank = bank;
-		threshold_restart_bank(&threshold_defaults, 0, 0);
+			high &= ~MASK_LVTOFF_HI;
+			high |= APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
+			wrmsr(address, low, high);
+			setup_APIC_extened_lvt(APIC_EXT_LVT_ENTRY_THRESHOLD,
+					       THRESHOLD_APIC_VECTOR,
+					       APIC_EXT_INT_MSG_FIX, 0);
+
+			threshold_defaults.address = address;
+			threshold_restart_bank(&threshold_defaults, 0, 0);
+
+		} while ((block ? (address)
+			        : (address = (low & MASK_BLKPTR_LO) >> 21)) &&
+			 (block ? (address++)
+			        : (address += MCG_XBLK_ADDR))               &&
+			 (++block < NR_BLOCKS));
 	}
 }
 
@@ -137,7 +178,8 @@ void __cpuinit mce_amd_feature_init(stru
  */
 asmlinkage void mce_threshold_interrupt(void)
 {
-	int bank;
+	u32 low, high, address;
+	unsigned int bank, block;
 	struct mce m;
 
 	ack_APIC_irq();
@@ -148,17 +190,42 @@ asmlinkage void mce_threshold_interrupt(
 	rdtscll(m.tsc);
 	m.cpu = smp_processor_id();
 
-	/* assume first bank caused it */
+	/* assume first register found caused the interrupt */
 	for (bank = 0; bank < NR_BANKS; ++bank) {
-		m.bank = MCE_THRESHOLD_BASE + bank;
-		rdmsrl(MSR_IA32_MC0_MISC + bank * 4, m.misc);
+		block = 0;
+		address = MSR_IA32_MC0_MISC + bank * 4;
 
-		if (m.misc & MASK_OVERFLOW) {
-			mce_log(&m);
-			goto out;
-		}
+		do {
+			if (rdmsr_safe(address, &low, &high))
+				continue;
+
+			if (!(high & MASK_VALID_HI)) {
+				if (block)
+					continue;
+				else
+					break;
+			}
+			    
+			if (!(high & MASK_VALID_HI >> 1)  ||
+			     (high & MASK_VALID_HI >> 2))
+				continue;
+
+			if (high & MASK_OVERFLOW_HI) {
+				rdmsrl(address, m.misc);
+				rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
+				       m.status);
+				m.bank = MCE_THRESHOLD_BASE + bank * NR_BLOCKS
+				       + block;
+				mce_log(&m);
+				goto out;
+			}
+		} while ((block ? (address)
+			        : (address = (low & MASK_BLKPTR_LO) >> 21)) &&
+			 (block ? (address++)
+			        : (address += MCG_XBLK_ADDR))               &&
+			 (++block < NR_BLOCKS));
 	}
-      out:
+out:
 	irq_exit();
 }
 
@@ -167,13 +234,11 @@ asmlinkage void mce_threshold_interrupt(
  */
 
 struct threshold_attr {
-        struct attribute attr;
-        ssize_t(*show) (struct threshold_bank *, char *);
-        ssize_t(*store) (struct threshold_bank *, const char *, size_t count);
+	struct attribute attr;
+	ssize_t(*show) (struct threshold_block *, char *);
+	ssize_t(*store) (struct threshold_block *, const char *, size_t count);
 };
 
-static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
-
 static cpumask_t affinity_set(unsigned int cpu)
 {
 	cpumask_t oldmask = current->cpus_allowed;
@@ -188,15 +253,15 @@ static void affinity_restore(cpumask_t o
 	set_cpus_allowed(current, oldmask);
 }
 
-#define SHOW_FIELDS(name) \
-        static ssize_t show_ ## name(struct threshold_bank * b, char *buf) \
-        { \
-                return sprintf(buf, "%lx\n", (unsigned long) b->name); \
-        }
+#define SHOW_FIELDS(name)                                          \
+static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
+{                                                                  \
+        return sprintf(buf, "%lx\n", (unsigned long) b->name);     \
+}
 SHOW_FIELDS(interrupt_enable)
 SHOW_FIELDS(threshold_limit)
 
-static ssize_t store_interrupt_enable(struct threshold_bank *b,
+static ssize_t store_interrupt_enable(struct threshold_block *b,
 				      const char *buf, size_t count)
 {
 	char *end;
@@ -213,7 +278,7 @@ static ssize_t store_interrupt_enable(st
 	return end - buf;
 }
 
-static ssize_t store_threshold_limit(struct threshold_bank *b,
+static ssize_t store_threshold_limit(struct threshold_block *b,
 				     const char *buf, size_t count)
 {
 	char *end;
@@ -236,18 +301,18 @@ static ssize_t store_threshold_limit(str
 	return end - buf;
 }
 
-static ssize_t show_error_count(struct threshold_bank *b, char *buf)
+static ssize_t show_error_count(struct threshold_block *b, char *buf)
 {
 	u32 high, low;
 	cpumask_t oldmask;
 	oldmask = affinity_set(b->cpu);
-	rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, low, high); /* ignore low 32 */
+	rdmsr(b->address, low, high);
 	affinity_restore(oldmask);
 	return sprintf(buf, "%x\n",
 		       (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
 }
 
-static ssize_t store_error_count(struct threshold_bank *b,
+static ssize_t store_error_count(struct threshold_block *b,
 				 const char *buf, size_t count)
 {
 	cpumask_t oldmask;
@@ -263,13 +328,13 @@ static ssize_t store_error_count(struct 
         .store = _store,                                      \
 };
 
-#define ATTR_FIELDS(name) \
-        static struct threshold_attr name = \
+#define RW_ATTR_FIELDS(name)        \
+static struct threshold_attr name = \
         THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
 
-ATTR_FIELDS(interrupt_enable);
-ATTR_FIELDS(threshold_limit);
-ATTR_FIELDS(error_count);
+RW_ATTR_FIELDS(interrupt_enable);
+RW_ATTR_FIELDS(threshold_limit);
+RW_ATTR_FIELDS(error_count);
 
 static struct attribute *default_attrs[] = {
 	&interrupt_enable.attr,
@@ -278,12 +343,12 @@ static struct attribute *default_attrs[]
 	NULL
 };
 
-#define to_bank(k) container_of(k,struct threshold_bank,kobj)
-#define to_attr(a) container_of(a,struct threshold_attr,attr)
+#define to_block(k) container_of(k, struct threshold_block, kobj)
+#define to_attr(a) container_of(a, struct threshold_attr, attr)
 
 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
 {
-	struct threshold_bank *b = to_bank(kobj);
+	struct threshold_block *b = to_block(kobj);
 	struct threshold_attr *a = to_attr(attr);
 	ssize_t ret;
 	ret = a->show ? a->show(b, buf) : -EIO;
@@ -293,7 +358,7 @@ static ssize_t show(struct kobject *kobj
 static ssize_t store(struct kobject *kobj, struct attribute *attr,
 		     const char *buf, size_t count)
 {
-	struct threshold_bank *b = to_bank(kobj);
+	struct threshold_block *b = to_block(kobj);
 	struct threshold_attr *a = to_attr(attr);
 	ssize_t ret;
 	ret = a->store ? a->store(b, buf, count) : -EIO;
@@ -310,27 +375,110 @@ static struct kobj_type threshold_ktype 
 	.default_attrs = default_attrs,
 };
 
+static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
+					       unsigned int bank,
+					       unsigned int block, 
+					       u32 address)
+{
+	int err;
+	u32 low, high;
+	struct threshold_block *b = NULL;
+
+	if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
+		return 0;
+
+	if (rdmsr_safe(address, &low, &high))
+		goto recurse;
+
+	if (!(high & MASK_VALID_HI)) {
+		if (block)
+			goto recurse;
+		else
+			return 0;
+	}
+			    
+	if (!(high & MASK_VALID_HI >> 1)  ||
+	     (high & MASK_VALID_HI >> 2))
+		goto recurse;
+
+	b = kmalloc(sizeof(struct threshold_block), GFP_KERNEL);
+	if (!b)
+		return -ENOMEM;
+	memset(b, 0, sizeof(struct threshold_block));
+
+	b->block = block;
+	b->bank = bank;
+	b->cpu = cpu;
+	b->address = address;
+	b->interrupt_enable = 0;
+	b->threshold_limit = THRESHOLD_MAX;
+
+	INIT_LIST_HEAD(&b->miscj);
+	
+	if (per_cpu(threshold_banks, cpu)[bank]->blocks)
+		list_add(&b->miscj,
+			 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
+	else
+		per_cpu(threshold_banks, cpu)[bank]->blocks = b;
+
+	kobject_set_name(&b->kobj, "misc%i", block);
+	b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
+	b->kobj.ktype = &threshold_ktype;
+	err = kobject_register(&b->kobj);
+	if (err)
+		goto out_free;
+recurse:
+	if (!block) {
+		address = (low & MASK_BLKPTR_LO) >> 21;
+		if (!address)
+			return 0;
+		address += MCG_XBLK_ADDR;
+	} else {
+		++address;
+	}
+
+	err = allocate_threshold_blocks(cpu, bank, ++block, address);
+	if (err)
+		goto out_free;
+
+	return err;
+
+out_free:
+	if (b) {
+		kobject_unregister(&b->kobj);
+		kfree(b);
+	}
+	return err;
+}
+
 /* symlinks sibling shared banks to first core.  first core owns dir/files. */
-static __cpuinit int threshold_create_bank(unsigned int cpu, int bank)
+static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 {
 	int err = 0;
 	struct threshold_bank *b = NULL;
+	cpumask_t oldmask = CPU_MASK_NONE;
+
+	down(&threshold_lock);
 
 #ifdef CONFIG_SMP
 	if (cpu_core_id[cpu] && shared_bank[bank]) {	/* symlink */
 		char name[16];
-		unsigned lcpu = first_cpu(cpu_core_map[cpu]);
-		if (cpu_core_id[lcpu])
+		unsigned first_core = first_cpu(cpu_core_map[cpu]);
+
+		if (cpu_core_id[first_core])
 			goto out;	/* first core not up yet */
 
-		b = per_cpu(threshold_banks, lcpu)[bank];
+		b = per_cpu(threshold_banks, first_core)[bank];
 		if (!b)
 			goto out;
+
 		sprintf(name, "threshold_bank%i", bank);
 		err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
 					&b->kobj, name);
 		if (err)
 			goto out;
+
+		b->sibling_count++;
 		per_cpu(threshold_banks, cpu)[bank] = b;
 		goto out;
 	}
@@ -343,38 +491,49 @@ static __cpuinit int threshold_create_ba
 	}
 	memset(b, 0, sizeof(struct threshold_bank));
 
-	b->cpu = cpu;
-	b->bank = bank;
-	b->interrupt_enable = 0;
-	b->threshold_limit = THRESHOLD_MAX;
 	kobject_set_name(&b->kobj, "threshold_bank%i", bank);
 	b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
-	b->kobj.ktype = &threshold_ktype;
 
 	err = kobject_register(&b->kobj);
-	if (err) {
-		kfree(b);
-		goto out;
-	}
+	if (err)
+		goto out_free;
+
 	per_cpu(threshold_banks, cpu)[bank] = b;
-      out:
+
+	oldmask = affinity_set(cpu);
+	err = allocate_threshold_blocks(cpu, bank, 0,
+					MSR_IA32_MC0_MISC + bank * 4);
+	affinity_restore(oldmask);
+
+	if (err)
+		goto out_free;
+
+	b->sibling_count++;
+	goto out;
+
+out_free:
+	per_cpu(threshold_banks, cpu)[bank] = NULL;
+	kfree(b);
+out:
+	up(&threshold_lock);
 	return err;
 }
 
 /* create dir/files for all valid threshold banks */
 static __cpuinit int threshold_create_device(unsigned int cpu)
 {
-	int bank;
+	unsigned int bank;
 	int err = 0;
 
 	for (bank = 0; bank < NR_BANKS; ++bank) {
 		if (!(per_cpu(bank_map, cpu) & 1 << bank))
 			continue;
+
 		err = threshold_create_bank(cpu, bank);
 		if (err)
 			goto out;
 	}
-      out:
+out:
 	return err;
 }
 
@@ -385,23 +544,50 @@ static __cpuinit int threshold_create_de
  *   of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  */
 
-/* cpu hotplug call removes all symlinks before first core dies */
+static __cpuinit void deallocate_threshold_block(unsigned int cpu,
+						 unsigned int bank)
+{
+	struct threshold_block *pos = NULL;
+	struct threshold_block *tmp = NULL;
+	struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
+
+	if (!head)
+		return;
+
+	list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
+		kobject_unregister(&pos->kobj);
+		list_del(&pos->miscj);
+		kfree(pos);
+	}
+
+	kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
+	per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
+}
+
 static __cpuinit void threshold_remove_bank(unsigned int cpu, int bank)
 {
 	struct threshold_bank *b;
 	char name[16];
 
+	down(&threshold_lock);
+
 	b = per_cpu(threshold_banks, cpu)[bank];
 	if (!b)
 		return;
-	if (shared_bank[bank] && atomic_read(&b->kobj.kref.refcount) > 2) {
+
+	if (shared_bank[bank] && b->sibling_count > 1) {
 		sprintf(name, "threshold_bank%i", bank);
 		sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
-		per_cpu(threshold_banks, cpu)[bank] = NULL;
+		b->sibling_count--;
 	} else {
+		deallocate_threshold_block(cpu, bank);
 		kobject_unregister(&b->kobj);
-		kfree(per_cpu(threshold_banks, cpu)[bank]);
+		b->sibling_count--;
+		kfree(b);
 	}
+
+	per_cpu(threshold_banks, cpu)[bank] = NULL;
+	up(&threshold_lock);
 }
 
 static __cpuinit void threshold_remove_device(unsigned int cpu)
@@ -411,6 +597,7 @@ static __cpuinit void threshold_remove_d
 	for (bank = 0; bank < NR_BANKS; ++bank) {
 		if (!(per_cpu(bank_map, cpu) & 1 << bank))
 			continue;
+
 		threshold_remove_bank(cpu, bank);
 	}
 }
@@ -419,19 +606,23 @@ static __cpuinit void threshold_remove_d
 static __cpuinit int threshold_create_symlinks(unsigned int cpu)
 {
 	int bank, err = 0;
-	unsigned int lcpu = 0;
+	unsigned int sibling = 0;
 
 	if (cpu_core_id[cpu])
 		return 0;
-	for_each_cpu_mask(lcpu, cpu_core_map[cpu]) {
-		if (lcpu == cpu)
+
+	for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
+		if (sibling == cpu)
 			continue;
+
 		for (bank = 0; bank < NR_BANKS; ++bank) {
 			if (!(per_cpu(bank_map, cpu) & 1 << bank))
 				continue;
+
 			if (!shared_bank[bank])
 				continue;
-			err = threshold_create_bank(lcpu, bank);
+
+			err = threshold_create_bank(sibling, bank);
 		}
 	}
 	return err;
@@ -441,18 +632,23 @@ static __cpuinit int threshold_create_sy
 static __cpuinit void threshold_remove_symlinks(unsigned int cpu)
 {
 	int bank;
-	unsigned int lcpu = 0;
+	unsigned int sibling = 0;
+
 	if (cpu_core_id[cpu])
 		return;
-	for_each_cpu_mask(lcpu, cpu_core_map[cpu]) {
-		if (lcpu == cpu)
+
+	for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
+		if (sibling == cpu)
 			continue;
+
 		for (bank = 0; bank < NR_BANKS; ++bank) {
 			if (!(per_cpu(bank_map, cpu) & 1 << bank))
 				continue;
+
 			if (!shared_bank[bank])
 				continue;
-			threshold_remove_bank(lcpu, bank);
+
+			threshold_remove_bank(sibling, bank);
 		}
 	}
 }
@@ -495,7 +691,7 @@ static int threshold_cpu_callback(struct
 	default:
 		break;
 	}
-      out:
+out:
 	return NOTIFY_OK;
 }
 
@@ -506,17 +702,17 @@ static struct notifier_block threshold_c
 static __init int threshold_init_device(void)
 {
 	int err;
-	int lcpu = 0;
+	int cpu = 0;
 
 	/* to hit CPUs online before the notifier is up */
-	for_each_online_cpu(lcpu) {
-		err = threshold_create_device(lcpu);
+	for_each_online_cpu(cpu) {
+		err = threshold_create_device(cpu);
 		if (err)
 			goto out;
 	}
 	register_cpu_notifier(&threshold_cpu_notifier);
 
-      out:
+out:
 	return err;
 }
 
diff -uparN linux.orig/include/asm-x86_64/mce.h linux/include/asm-x86_64/mce.h
--- linux.orig/include/asm-x86_64/mce.h	2006-05-17 11:23:17.000000000 -0500
+++ linux/include/asm-x86_64/mce.h	2006-05-17 11:26:15.000000000 -0500
@@ -67,8 +67,17 @@ struct mce_log { 
 /* Software defined banks */
 #define MCE_EXTENDED_BANK	128
 #define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0
-#define MCE_THRESHOLD_BASE      MCE_EXTENDED_BANK + 1 /* MCE_AMD */
-#define MCE_THRESHOLD_DRAM_ECC  MCE_THRESHOLD_BASE + 4
+
+#define MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
+
+#define MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
+#define MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
+#define MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
+#define MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
+#define MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
+#define MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
+
+#define MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
 
 #ifdef __KERNEL__
 #include <asm/atomic.h>





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